器件名称: W3E32M64S-200SBI
功能描述: 32Mx64 DDR SDRAM
文件大小: 723.96KB 共17页
简 介:White Electronic Designs
32Mx64 DDR SDRAM
FEATURES
DDR SDRAM rate = 200, 250, 266, 333** Package: 208 Plastic Ball Grid Array (PBGA), 13 x 22mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CLK Four internal banks for concurrent operation Data mask (DM) pins for masking write data (one per byte) Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, Industrial and Military TemperatureRanges Organized as 32M x 64 Can be user organized as 2x32Mx32 or 4x32Mx16 Weight: W3E32M64S-XSBX — 1.5 grams typical
W3E32M64S-XSBX
BENEFITS
73% Space Savings vs. FPBGA 43% Space Savings vs TSOP Reduced part count 21% I/O reduction vs TSOP 13% I/O reduction vs FPBGA Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match Upgradeable to 64M x 64 density (contact factory for information)
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containin……
