器件名称: W3E16M64S-266BC
功能描述: 16Mx64 DDR SDRAM
文件大小: 709.38KB 共16页
简 介:White Electronic Designs
16Mx64 DDR SDRAM
FEATURES
DDR Data Rate = 200, 250, 266Mbps Package: 219 Plastic Ball Grid Array (PBGA), 21 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CLK and CLK#) Commands entered on each positive CLK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CLK Four internal banks for concurrent operation Two data mask (DM) pins for masking write data Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, Industrial and Military Temperature Ranges Organized as 16M x 64 Weight: W3E16M64S-XBX - 2 grams typical
* This product is subject to change without notice.
W3E16M64S-XBX
BENEFITS
50% SPACE SAVINGS Reduced part count Reduced I/O count 17% I/O Reduction Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match Upgradeable to 32M x 64 density (W3E32M64S-XBX)
GENERAL DESCRIPTION
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containing 268,435,456 bits. Each chip is internally congured as a quad-bank DRAM. Each of the chip’s 67,108……
