器件名称: W25S243A-12
功能描述: 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
文件大小: 303.01KB 共17页
简 介:Preliminary W25S243A 64K × 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W25S243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 × 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduces power dissipation. This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
Synchronous operation High-speed access time: 12 nS Single +3.3V power supply Individual byte write capability 3.3V LVTTL compatible I/O Clock-controlled and registered input Asynchronous output enable
Pipelined/non-pipelined data output capability Supports snooze mode (low-power state) Internal burst counter supports Intel burst (Interleaved) mode & linear burst mode Supports 2T/1T mode Packaged in 128-pin QFP and TQFP
BLOCK DIAGRAM
A(15:0)
INPUT REGISTER 64K X 64 CORE ARRAY
CLK CE(3:1) GW BWE BW(8:1) OE ADSC ADSP ADV LBO FT ZZ CONTROL LOGIC REGISTER DATA I/O REGISTER I/O(64:1)
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Publication Release Date: November 1998 Revision A1
Preliminary W25S243A
PIN CONFIGURATION
V D C D NEN Q C2 C 1 1 2 2 8 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 3 9
/ / / / / CV V/ B BB B/ C E S D C W……
