器件名称: W25P022A-6
功能描述: 64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
文件大小: 310.25KB 共17页
简 介:W25P022A 64K × 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W25P022A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM organized as 65,536 × 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode reduces power dissipation. The W25P022A supports both 2T/2T mode and 2T/1T mode, which can be selected by pin 42. The default mode is 2T/1T, with pin 42 low. To switch to 2T/2T mode, bias pin 42 to VDDQ. The state of pin 42 should not be changed after power up. The 2T/2T mode will sustain one cycle of valid data output in a burst read cycle when the device is deselected by CE2/ CE3 . This mode supports 3-1-1-11-1-1-1 in a two-bank, back-to-back burst read cycle. On the other hand, the 2T/1T mode disables data output within one cycle in a burst read cycle when the device is deselected by CE2/ CE3 . In this mode, the device supports only 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
Synchronous operation High-speed access time: 6/7 nS (max.) Single +3.3V power supply Individual byte write capability 3.3V LVTTL compatible I/O Clock-controlled and registered input Asynchronous output enable
Pipelined/non-pipelined data output capability Supports snooze mode (lo……
