W232_02

器件名称: W232_02

功能描述: Ten Output Zero Delay Buffer

文件大小: 106.2KB 共6页

生产厂商: CYPRESS

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简　　介:W232 Ten Output Zero Delay Buffer Features Well-suited to both 100- and 133-MHz designs Ten/eleven LVCMOS/LVTTL outputs 3.3V power supply Available in 24-pin TSSOP package Key Specifications Operating Voltage: .............................................. 3.3V ± 10% Operating Range: ........................25 MHz < fOUT < 140 MHz Cycle-to-Cycle Jitter: ...............................................< 150 ps Output to Output Skew: ...........................................< 100 ps Phase Error Jitter: ....................................................< 125 ps Static Phase Error: ...................................................< 150 ps Block Diagram Pin Configurations FBIN CLK PLL FBOUT Q0 Q1 Q2 AGND VDD Q0 Q1 Q2 GND GND Q3 Q4 VDD OE0:4 FBOUT 1 2 3 4 24 23 22 21 CLK AVDD VDD Q8 Q7 GND GND Q6 Q5 VDD OE5:8 FBIN W232-09 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 OE0:4 Q3 OE Q4 Q5 OE5:8 Q6 Q7 Q8 Q9 Configuration of these blocks dependent upon specific option being used. AGND VDD Q0 Q1 Q2 GND GND Q3 Q4 VDD OE FBOUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK AVDD VDD Q9 Q8 GND GND Q7 Q6 Q5 VDD FBIN W232-10 Cypress Semiconductor Corporation Document #: 38-07167 Rev. *B 3901 North First Street San Jose CA 95134 408-943-2600 Revised December 15, 2002 W232 Pin Definitions Pin Name CLK FBIN Pin No. (-09) 24 13 Pin No. (-10) 24 13 Pin Type I I Pin Description Reference Input: Output signals Q0:9 will be synchronized to this……