器件名称: AD9211-200EB
功能描述: 10-Bit, 170/200/250 MSPS 1.8 V A/D Converter
文件大小: 296.21KB 共21页
简 介:Preliminary Technical Data
FEATURES
SNR = 60 dBFs @ fIN up to 70 MHz @ 250 MSPS ENOB of 9.7 @ fIN up to 70 MHz @ 250 MSPS (–0.5 dBFS) SFDR = 80 dBc@ fIN up to 70 MHz @ 250 MSPS (–0.5 dBFS) Excellent Linearity DNL = ±0.3 LSB (Typical) INL = ±0.5 LSB (Typical) LVDS at 250 MSPS (ANSI-644 levels) 900 MHz Full Power Analog Bandwidth On-Chip Reference and Track-and-Hold Power Dissipation = 380 mW Typical @ 250 MSPS 1.25 V Input Voltage Range 1.8 V Analog Supply Operation Output Data Format Option Data Clock Output Provided Clock Duty Cycle Stabilizer
10-Bit, 170/200/250 MSPS 1.8 V A/D Converter AD9211
AGND AVDD (1.8V) DrVDD (1.8V) DGND (Pin 0) ADC 10 10-bit Core Output 10 Staging LVDS D9-D0 (D4-D0 DDR mode) OTR+ OTRSerial Port DCO+ DCORESET SCLK SDIO CSB
AD9211
Ref VIN+ VINT/H
CLK+ CLK-
Clock Mgmt
Figure 1. Functional Block Diagram
APPLICATIONS
Wireless and Wired Broadband Communications Cable Reverse Path Communications Test Equipment Radar and Satellite Subsystems Power Amplifier Linearization
Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead chip scale package (56 LFCSP) specified over the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. 2. 3. High Performance—Maintains 60 dB SNR @ 250 MSPS with a 65 MHz input. Low Power—Consumes only 380mW @ 250 MSPS. Ease of Use—LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample/hold provide flexibility in system design. Us……
