器件名称: 74ALVCH16831DBBRE4
功能描述: 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
文件大小: 131.85KB 共9页
简 介:www.ti.com
SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
SCES083F – AUGUST 1996 – REVISED SEPTEMBER 2004
FEATURES
Member of the Texas Instruments Widebus Family Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
DBB PACKAGE (TOP VIEW)
DESCRIPTION/ORDERING INFORMATION
This 1-bit to 4-bit address register/driver is designed for 1.65-V to 3.6-V VCC operation. The device is ideal for use in applications in which a single address bus is driving four separate memory locations. The SN74ALVCH16831 can be used as a buffer or a register, depending on the logic level of the select (SEL) input. When SEL is logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by the two output-enable (OE) controls. Each OE controls two groups of nine outputs. When SEL is logic low, the device is in the register mode. The register is an edge-triggered D-type flip-flop. On the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers. OE controls operate the same as in buffer mode. When OE is logic low, the outputs are in a normal logic state (high or low logic level). When OE is logic high, the outputs are in the high-impedance state. SEL and OE do not affect the internal ope……
