器件名称: MSA24
功能描述: Octal Registered Transceiver
文件大小: 78.98KB 共7页
简 介:74F543 Octal Registered Transceiver
April 1988 Revised October 2000
74F543 Octal Registered Transceiver
General Description
The F543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The A outputs are guaranteed to sink 24 mA while the B outputs are rated for 64 mA.
Features
s 8-bit octal transceiver s Back-to-back registers for storage s Separate controls for data flow in each direction s A outputs sink 24 mA s B outputs sink 64 mA
Ordering Code:
Order Number 74F543SC 74F543MSA 74F543PC 74F543SPC Package Number M24B MSA24 N24A N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
2000 Fairchild Semiconductor Corporation
DS009554
www.fairchildsemi.com
74F543
Unit Loading/Fan Out
U.L. Pin Names OEAB OEBA CEAB CEBA LEAB LEBA A0–A7 Description HIGH/LOW A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B En……
