器件名称: P580-30DC
功能描述: 38MHz-640MHz Low Phase Noise VCXO
文件大小: 251.79KB 共9页
简 介:(Preliminary)
PL580-30
38MHz-640MHz Low Phase Noise VCXO
FEATURES
Less than 0.4ps RMS (12KHz-20MHz) phase jitter for all frequencies . Low phase noise output (@ 1MHz frequency offset -140dBc/Hz for 311.04MHz, -131dBC/Hz for 622.08MHz 19MHz-40MHz crystal input. 38MHz-640MHz output. Selectable PECL, LVDS, or CMOS outputs. No external varicap required. Output Enable selector. Wide pull range (+/-200ppm). 3.3V operation. Available in 3x3 QFN or 16-pin TSSOP packages.
DIE CONFIGURATION
65 mil
OUTSEL0v
OUTSEL1^
VDDOSC
VDDANA
VDDANA
VDDDIG
SEL0^
SEL1^
(1550,1475)
17 16
25
24
23
22
21
20
19
18
GNDBUF CMOS LVDSB PECLB VDDBUF VDDBUF PECL LVDS OE_SEL^
XIN XOUT SEL2
62 mil
26
Die ID: 2222-22A
27
15
28
14
13
DNC
29
12
11
OE_CTRL
30
DESCRIPTION
The PL580-30 is a monolithic low jitter and low phase noise VCXO, capable of 0.4ps RMS phase jitter and PECL, LVDS, or CMOS outputs, covering a wide frequency output range up to 640MHz. It allows the control of the output frequency with an input voltage (VCON), using a low cost crystal. The PL580-30 is designed to address the demanding requirements of high performance applications such as SONET, GPS, XDSL, etc.
VCON
31 1
C502A
10 9
2
3
4
5
6
7
8
GNDOSC
GNDANA
Y X
(0,0)
Note1: ^ Denotes internal pull up resistor.
DIE SPECIFICATIONS
Name Size Reverse side Pad dimensions Thickness Value 62 x 65 mil GND 80 micron x 80 micron 10 mil
BLOCK DIAGRAM
VCON
VARICAP
VCO Divider Charge Pump + Loop……
