器件名称: P500-17TCL
功能描述: Low Phase Noise VCXO (17MHz to 36MHz)
文件大小: 208.98KB 共6页
简 介:PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
FEATURES
VCXO output for the 17MHz to 36MHz range Low phase noise (-130 dBc @ 10kHz offset at 35.328MHz). CMOS output with OE tri-state control. 17 to 36MHz fundamental crystal input. Integrated high linearity variable capacitors. 12mA drive capability at TTL output. +/- 150 ppm pull range, max 5% (typ.) linearity. Low jitter (RMS): 2.5ps period jitter. 2.5 to 3.3V operation. Available in 8-Pin SOIC, 6-pin SOT23 GREEN / RoHS compliant packages, or DIE.
PIN CONFIGURATION
XIN VDD* VCON GND
1 2 3 4
8 7 6 5
XOUT OE^ VDD* CLK
SOIC-8
PLL500-17
1 2 3 6 5 4
XOUT GND
XIN VDD VCON
P500-17
DESCRIPTION
The PLL500-17 is a low cost, high performance and low phase noise VCXO for the 17 to 36MHz range, providing less than -130dBc at 10kHz offset at 35.328MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 17 to 36MHz (fundamental resonant mode).
CLK
SOT23-6
^: Denotes internal Pull-up *: Only one VDD pin needs to be connected
BLOCK DIAGRAM
XIN XOUT
XTAL OSC VARICAP
CLK OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/08/06 Page 1
PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
DIE PAD LAYOUT DIE SPECIFICATIONS
Name
OE^ 7
39 mil
32 mil
(812,986)
8 1 XIN XOUT
Value
2
VDD VDD 6
Size Reverse side Pad dimensions Thickness
39 x 32……
