器件名称: PLL620-00DI
功能描述: Low Phase Noise XO with multipliers (for HF Fund. and 3rd O.T.)
文件大小: 208.31KB 共7页
简 介:PLL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3 rd O.T.) FEATURES
100MHz to 200MHz Fundamental or 3 rd Overtone Crystal input. Output range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier) or 400 – 700MHz (4x multiplier). Available outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output). Supports 3.3V-Power Supply. Available in die form. Thickness 10 mil.
DIE CONFIGURATION 65 mil
OUTSEL0^ OUTSEL1^ SEL0^ SEL1^ VDD VDD VDD VDD
(1550,1475)
17 16
25
24
23
22
21
20
19
18
GNDBUF CMOS LVDSB PECLB VDDBUF VDDBUF PECL LVDS OE_SEL^
XIN XOUT SEL3^
62 mil
26
27
Die ID: A1010-10A
15
28
14
SEL2^ OE CTRL NC
13 29 12 11 30
DESCRIPTION
The PLL620-00 is an XO IC specifically designed to work with high frequency fundamental and third overtone crystals. Its design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. It is ideal for XO applications requiring LVDS or PECL output levels at high frequencies.
C502A
31 1 2 3 4 5 6 7 8
10 9
Y
(0,0)
X
OUTPUT SELECTION AND ENABLE
OUTSEL1 (Pad #18) 0 0 1 1 OE_SELECT (Pad #9) OUTSEL0 (Pad #25) 0 1 0 1 OE_CTRL (Pad #30) 0 1 (Default) 0 (Default) 1 Selected Output High Drive CMOS Standard CMOS LVDS PECL (default) State Tri-state Output enabled Output enabled Tri-state
DIE SPECIFICATIONS
Name Size Reverse side Pad dimensions Thi……
