器件名称: MC14042BFEL
功能描述: Quad Transparent Latch
文件大小: 174.58KB 共8页
简 介:MC14042B Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic “0” state, data is transferred during the low clock level, and when the polarity input is in the logic “1” state the transfer occurs during the high clock level.
http://onsemi.com MARKING DIAGRAMS
16 PDIP–16 P SUFFIX CASE 648 MC14042BCP AWLYYWW 1 16 SOIC–16 D SUFFIX CASE 751B 1 16 SOEIAJ–16 F SUFFIX CASE 966 Unit V V mA mW A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week 1 MC14042B AWLYWW 14042B AWLYWW
Buffered Data Inputs Common Clock Clock Polarity Control Q and Q Outputs Double Diode Input Protection Supply Voltage Range = 3.0 Vdc to 1 8 Vdc Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, ……
