器件名称: MC14042BDR2G
功能描述: Quad Transparent Latch
文件大小: 100.81KB 共8页
简 介:MC14042B Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic “0” state, data is transferred during the low clock level, and when the polarity input is in the logic “1” state the transfer occurs during the high clock level.
Features
http://onsemi.com MARKING DIAGRAMS
PDIP16 P SUFFIX CASE 648 16 MC14042BCP AWLYYWWG 1
Buffered Data Inputs Common Clock Clock Polarity Control Q and Q Outputs Double Diode Input Protection Supply Voltage Range = 3.0 Vdc to 1 8 Vdc Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range PbFree Packages are Available*
16 SOIC16 D SUFFIX CASE 751B 1 14042BG AWLYWW
16 SOEIAJ16 F SUFFIX CASE 966 1 A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = PbFree Indicator MC14042B ALYWG
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient)……
