器件名称: MG2RT
功能描述: Rad Tolerant 350K Used Gates 0.5
文件大小: 211.76KB 共13页
简 介:Features
Full Range of Matrices with up to 480K Gates 0.5 m Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG) 3 and 5 Volts Operation; Single or Dual Supply Mode High Speed Performances: – 450 ps Max NAND2 Propagation Delay at 4.5V, 720 ps at 2.7V and FO = 5 – Min 610 MHz Toggle Frequency at 4.5V, 320 MHz at 2.7V Programmable PLL Available upon Request High System Frequency Skew Control through Clock Tree Synthesis Software Low Power Consumption: – 1.96 W/Gate/MHz at 5V – 0.6 W/Gate/MHz at 3V Integrated Power On Reset Matrices with a Max of 484 Fully Programmable Pads Standard 3, 6, 12 and 24 mA I/Os Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator CMOS/TTL/PCI Interface ESD (2 kV) and Latch-up Protected I/O High Noise and EMC Immunity: – I/O with Slew Rate Control – Internal Decoupling – Signal Filtering between Periphery and Core – Application Dependent Supply Routing and Several Independant Supply Sources Wide Selection of MQFPs and MCGA Packages up to 472 Pins Delivery in Die Form with 94.6 m Pad Pitch Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management Cadence, Mentor, Vital and Synopsys Reference Platforms EDIF and VHDL Reference Formats Available in Military and Space Quality Grades (SCC, MIL-PRF-38535) No Single Event Latch-up below an LET threshold of 80MeV/mg/cm2 Tested up to a Total Dose of 60 Krad (……
