器件名称: IZ4027B
功能描述: Dual JK Flip-Flop
文件大小: 48.07KB 共6页
简 介:TECHNICAL DATA
IW4027B
Dual JK Flip-Flop
The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and Set are independent and override the J, K, or Clock inputs. The outputs are buffered for best system performance. Operating Voltage Range: 3.0 to 18 V Maximum input current of 1 A at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply
ORDERING INFORMATION IW4027BN Plastic IW4027BD SOIC IZ4027B Chip TA = -55° to 125° C for all packages
PIN ASSIGNMENT LOGIC DIAGRAM
FUNCTION TABLE
Inputs Set Reset Clock L H H L L L PIN 16 =VCC PIN 8 = GND L H L H L L L L X X X J X X X L H L H K X X X L L H H Outputs Qn+1 L H H Qn+1 H L H
No change H L Qn L H Qn
X = don’t care Qn+1 = State After Clock Positive Transition
INTEGRAL
1
IW4027B
MAXIMUM RATINGS *
Symbol VCC VIN IIN PD Ptot Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP, SOIC Package Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +20 -0.5 to VCC +0.5 ±10 500** 100 ……
