器件名称: FX629J
功能描述: Delta Modulation Codec
文件大小: 93.31KB 共10页
简 介:CML Semiconductor Products
PRODUCT INFORMATION
FX629
Features/Applications Designed to Meet Mil-Std-188-113 Military Communications Delta MUX, Switch and Phone Applications Single-Chip Full-Duplex Codec On-Chip Input and Output Filters
DATA ENABLE ENCODER FORCE IDLE
Delta Modulation Codec
Publication D/629/2 July 1994 Provisional Issue
Programmable Sampling Clocks 3 or 4-bit Compand Algorithm Forced Idle Facility Powersave Facility Single 5V CMOS Process Full-Duplex CVSD* Codec
ENCODER INPUT VDD V SS XTAL/CLOCK XTAL ENCODER DATA CLOCK DECODER DATA CLOCK VBIAS MODE 1 MODE 2 ALGORITHM POWERSAVE DECODER INPUT DEMOD DECODER OUTPUT DECODER FORCE IDLE CLOCK MODE LOGIC SAMPLING RATE CONTROL MOD ENCODER OUTPUT
f1 f0
CLOCK RATE GENERATORS
f2
FX629
3 or 4-BIT
f3
f1
Fig.1 Internal Block Diagram
Brief Description
The FX629 is an LSI circuit designed as a *Continuously Variable Slope Delta Codec and is intended for use in military communications systems. Designed to meet Mil-Std-188-113 with external components, the device is suitable for applications in military Delta Multiplexers, switches and phones. Encoder input and decoder output filters are incorporated on-chip. Sampling clock rates can be programmed to 16, 32 or 64 k bits/second from an internal clock generator or may be externally applied in the range 8 to 64 k bits/ second. Sampling clock frequencies are output for the synchronization of external circuits. The encoder has an enable function for use in multiplexer appl……
