器件名称: FDG6322C
功能描述: Dual N & P Channel Digital FET
文件大小: 674.29KB 共9页
简 介:June 2008
FDG6322C Dual N & P Channel Digital FET
General Description
These dual N & P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.
Features
N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 @ VGS= 4.5 V, RDS(ON) = 5.0 @ VGS= 2.7 V. P-Ch -0.41 A,-25V, RDS(ON) = 1.1 @ VGS= -4.5V, RDS(ON) = 1.5 @ VGS= -2.7V. Very small package outline SC70-6. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model).
SC70-6
SOT-23
SuperSOTTM-6
SOT-8
SO-8
SOIC-14
G2 D1
S2
1
Q1
6
2
pin 1
5
Q2
SC70-6
Mark: .22
S1
G1
D2
3
4
Absolute Maximum Ratings
Symbol Parameter
TA = 25oC unless other wise noted
N-Channel P-Channel Units
VDSS VGSS ID
Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed
25 8 0.22 0.65
(Note 1)
-25 -8 -0.41 -1.2 0.3 -55 to 150 6
V V A
PD TJ,TSTG ESD
Maximum Power Dissipation
W °C kV
Operating and Storage Temperature Range Electrostatic Discharge Rating MIL-STD-883D Human……
