器件名称: CS2100-CP-CZZ
功能描述: Fractional-N Clock Multiplier
文件大小: 412.58KB 共32页
简 介:CS2100-CP
Fractional-N Clock Multiplier
Features
Clock Multiplier / Jitter Reduction
General Description
The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-CP is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock at frequencies as low as 50 Hz. The CS2100-CP supports both IC and SPI for full software control. The CS2100-CP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) grade. Customer development kits are also available for device evaluation. Please see “Ordering Information” on page 32 for complete details.
Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source Highly Accurate PLL Multiplication Factor – Maximum Error Less Than 1 PPM in HighResolution Mode IC / SPI Control Port Configurable Auxiliary Output Flexible Sourcing of Reference Clock – External Oscillator or Clock Source – Supports Inexpensive Local Crystal Minimal Board Space Required – No External Analog Loop-filter Components
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3.3 V
Timing Reference Frequency Reference PLL Output Lock Indicator
IC/SPI Software Control
IC / SPI
Auxiliary Output
8 MHz to 75 MHz Low-Jitter Timing Reference
Fractional-N Frequency Synthesizer
6 to 75 MHz PLL Output
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