器件名称: M74HCT74RM13TR
功能描述: DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
文件大小: 432.54KB 共10页
简 介:M74HCT74
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
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HIGH SPEED : fMAX = 48MHz (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC =2A(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) BALANCED PROPAGATION DELAYS: tPLH tPHL SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74
DIP
SOP
TSSOP
ORDER CODES
PACKAGE DIP SOP TSSOP TUBE M74HCT74B1R M74HCT74M1R T&R M74HCT74RM13TR M74HCT74TTR
DESCRIPTION The M74HCT74 is an high speed CMOS DUAL D TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. A signal on the D INPUT (nD) is transferred on the Q OUTPUT during the positive going transition of the clock pulse. CLEAR (CLR) and PRESET (PR) are independent of the clock and accomplished by a low on the appropriate input.
The M74HCT74 is designed to directly interface HSC2MOS systems with TTL and NMOS components. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
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M74HCT74
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1,13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK 1PR, 2PR 1Q, 2Q 1Q, 2Q GND Vcc NAME AND FUNCTION Asynchronous Reset Direct Input Data Inputs Clock Input (LOW-to-HIGH, Edge-Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage
TRUTH TABLE
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