器件名称: F_USB20LP
功能描述: Standard Bus IP: High Speed USB 2.0 Device Controller
文件大小: 82.47KB 共2页
简 介:Standard Bus IP: High Speed USB 2.0 Device Controller
Fujitsu Macro
F_USB20LP
PHY LINK CPU
End-Point FIFO
Interrupt
Protocol Engine (UDC-20)
Local Bus Interface
Local CPU Bus (32bit)
Internal Bus
PHY
RAM
USB
UTMI
Control Status Register
ROM
Features
Full compliance with USB 2.0 Device Controller standard Integrated PHY macro for system cost reduction and space saving Supports high-speed (480Mbps) and full-speed (12Mbps) Customize endpoint numbers and configurations UTMI (USB2.0 Transceiver Macrocell Interface)
Description
Link
Protocol Engine (UDC-20) is a fully synthesizable soft core that supports high-speed (480 Mbps), full-speed (12Mbps) signaling bit rates. Protocol engine reduces CPU burden by processing basic USB 2.0 protocols in hardware. Endpoint numbers, configurations, and its FIFO densities are flexible. Following is one of the configuration examples. 1) End Point 0 2) End Point 0 3) End Point 1 4) End Point 2 5) End Point 3 control out control in Bulk out Bulk in Interrupt in 64Byte 64Byte 512Byte (Double buffer) 512Byte (Double buffer) 64Byte
Overview
Fujitsu USB 2.0 device controller is a synthesizable core suitable for different process. Corresponding physical interface in 0.18um and 0.11um technology (supporting high and full speed operation) also available for integration. Generic CPU interface makes it easy to be integrated into overall ASIC. Different endpoints are available for application such as printer, scanner, digital still camera, bl……
